(1) Field of the Invention
The invention relates to a combination of an upper die and a lower die that guides small diameter test pins in semiconductor test equipment, such as a vertical pin probing device. More particularly, the upper die and the lower die have an apertured frame portion formed by laminating a plurality of relatively thin metallic layers of a low coefficient of thermal expansion (CTE) alloy. A low CTE ceramic insert having an array of holes seals the aperture and guides the small diameter test pins.
(2) Description of the Related Art
The manufacture of integrated circuits has progressed to where on the order of hundreds of individual integrated circuit (IC) chips are formed by photolithography on a single, relatively large, on the order of 8 inch in diameter silicon wafer. After manufacture and test, the individual chips are singulated for assembly into individual devices. Since it is easier to handle the relatively large silicon wafers, functionality testing of the chips is preferably conducted prior to singulation. A number of test devices are available to test the chips on the wafer. Integrated circuits in their wafer state are tested using probing devices, the probes of which are traditionally of cantilevered or vertical configuration. In a known type of vertical pin probing device, the probes are held between spaced upper and lower dies and are generally curved with a straight portion that protrudes substantially perpendicular through the lower die of the housing. As the wafer under test is raised into contact with the probing device, and then overdriven a few thousandths of an inch, the probes recede into the housing and the curved portion of the probe deflects causing spring force that provides good electrical contact with the integrated circuit pads.
Traditionally, the housing that guides the probe pins is made from a dielectric material, often a plastic such as Delrin(copyright), trademark of E.I. dupont de Nemours and Co, Wilmington, Del. A number of IC test protocols involve testing chip functionality at two or more different temperatures, for example, 0xc2x0 C. and 135xc2x0 C. (32xc2x0 F. and 275xc2x0 F.). The plastic prior art probe housing expands with a significantly higher thermal expansion rate than that of the silicon base material of the IC wafer under test. The expansion differential causes a mismatch of the probe locations and the IC pad locations, a condition that not only results in failure to make satisfactory electrical contact, but may result in fatal damage to the IC due to probe penetration in the circuit region of the IC.
One solution to this problem is to dimensionally compensate the room temperature pitch dimensions of probes in the housing so that at the specified test temperature it will have expanded to provide a nearly exact match of probe and pad positions. Except for temperatures within a narrow range, this option requires separate probe devices for each specific temperature, thus greatly increasing the user""s monetary investment in probe devices.
Another solution would be to find a plastic or other suitable dielectric that matches the coefficient of thermal expansion of the silicon wafer. To date, however, the most practical choices of dielectric materials have expansion rates much higher than silicon. Plastics generally have a limited high temperature capability, thereby preventing their uses -for high temperature probing of IC""s.
U.S. Pat. No. 6,163,162 entitled, xe2x80x9cTemperature Compensated Vertical Pin Probing Devicexe2x80x9d discloses forming the portion of the housing that guides the pins from a low CTE metal, Invar. Invar is a trademark of Imphy, S.A. Invar is an alloy having a nominal composition, by weight, of 36% nickel and 64% iron and a CTE that is approximately equal to that of silicon.
Invar is electrically conductive. To prevent the housing from electrically shorting the pins, the patent discloses coating the pin guiding recesses with a dielectric such as a polymer or ceramic. The dielectric may be disposed into the recesses as either a coating or as an insert. A disclosed polymer is Vespel(copyright), a trademark of DuPont. A disclosed ceramic is Macor(copyright), a trademark of Corning Glass Works, Corning, N.Y. Typically, if the dielectric is a ceramic, an anti-stick coating is applied to the ceramic. A suitable anti-stick coating is disclosed to be XYLAN(copyright) manufactured by Whitford Corporation.
U.S. Pat. No. 6,297,657 entitled, xe2x80x9cTemperature Compensated Vertical Probing Devicexe2x80x9d discloses that rather than the die housing being a machined block of Invar, multiple layers of Invar foil may be coated with an adhesive and laminated together to form the die housing. This construction is also electrically conductive and requires the pin guiding recesses to be coated with a suitable dielectric. The disclosures of the 6,163,162 patent and of the 6,297,657 patent are both incorporated by reference in their entireties herein.
Spacing between circuit traces on the chips under test are on the order of a few microns. As a result, the probe head assembly has extremely tight tolerances. The frame must be extremely flat and accurately machined. This has proven cumbersome for large Invar frames having a thickness on the order of 0.1 inch that may further contain machined pockets with a depth on the order of 0.09 inch for holding up to 4000 probes with a 0.006 inch pitch. In addition to the time and expense associated with complex, traditional machining processes, removing large amounts of metal across a thin frame tends to stress and deform the frame resulting in high rates of rejection for the finished machined part.
There therefore exists a need for a relatively low-cost process for the manufacture of probe card frames characterized by precision forming, a low rate of rejection and a substantial absence of internal stresses imparted by machining.